Polyphase Filter Approach for High Performance, FPGA-Based Quadrature Demodulation

The polyphase filter approach to quadrature demodulation is presented. It is shown to be well suited for the implementation of purpose-designed high performance, wide bandwidth quadrature demodulators in low-cost Field-Programmable Gate Array (FPGA) technology. The duplicated polyphase filter approach is introduced, as a way to increase the maximum allowable input signal bandwidth while maintaining a processing rate compatible with FPGA implementation. Other algorithmic considerations are discussed, and architectural considerations specifically applicable to the realization of digital filtering in FPGAs are discussed. A design example suitable for processing input signals centered on an intermediate frequency of 160 MHz with a bandwidth of ~45 MHz is presented. This design occupies 83% of the Configurable Logic Blocks (CLBs) in a low-cost Xilinx X4010E-3 FPGA. Additional techniques for further performance optimization are presented.